1. Field of Invention
The present invention relates to a chip package without a core and stacked package structure thereof. More particularly, the present invention relates to a chip package having small thickness and without a core, and stacked package structure thereof.
2. Description of Related Art
In the information era today, users prefer electronic products with high speed, high quality and versatile functions. In terms of product appearance, the design of the electronic products tends to be lighter, thinner, shorter and smaller. In order to achieve the above aspects, many companies have incorporated a systematic concept in the circuit design. Accordingly, the single chip can have versatile functions to reduce the number of the chips disposed in the electronic products. Moreover, in the technology of electronic package, in order to meet the light, thin, short and small design trend, the package design concept of the of multi-chip module (MCM), chip scale package (CSP) and stacked multi-chip have been developed. The following is a description of several conventional chip package structures.
FIG. 1 is a cross-sectional diagram of a conventional stacked chip package structure. Referring to FIG. 1, the conventional stacked chip package structure 50 includes a package substrate 100 and multiple chip packages 200a, 200b, wherein the chip packages 200a, 200b stacked on the circuit substrate 100 are electrically connected to the circuit substrate 100. Each of the chip packages 200a, 200b includes a package substrate 210, a chip 220, multiple bumps 230, an under fill 240 and multiple solder balls 250. The chip 220 and the bumps 230 are disposed on the package substrate 210, the bumps 230 are disposed between the chip 220 and the package substrate 210, and the chip 220 is electrically connected to the package substrate 210 via the bumps 230. The under fill 240 disposed between the chip 220 and the package substrate 210 cover these bumps 230.
The package substrate 210 has multiple conductive poles 212 and multiple bonding pads 214, wherein each conductive pole 212 passes through the package substrate 210, and each bonding pad 214 is disposed on the conductive pole 212. Moreover, each solder ball 250 is disposed on the bonding pad 214. Accordingly, the chip package 200a is electrically connected to the chip package 200b by the solder ball 250, and the chip package 200b is electrically connected to the circuit substrate 100 by the solder ball 250.
In general, in the manufacturing method of the package substrate 210, the core dielectric layer is used as the core material, the patterned circuit layer and the patterned dielectric layer are inter-stacked on the core dielectric layer in a fully additive process, semi-additive process, subtractive process or other process. Accordingly, the core dielectric layer may take a major proportion in the entire thickness of the package substrate 210. Therefore, if the thickness of the core dielectric layer can not be reduced effectively, it would be a big obstacle in reducing the thicknesses of the chip package 200a and 200b. 
Of course, when a bottleneck is met in the reduction of the thicknesses of the chip package 200a and 200b, the entire thickness of the stacked chip package structure 50 cannot be effectively reduced, such that the package integrity of the stacked chip package structure 50 cannot be improved effectively.